Conventionally, various types of signal process devices use a storage device containing a FIFO (First-in-First-out) memory such as a line buffer included in an image processing apparatus.
A technique for speeding operation of a FIFO memory is disclosed in Patent Literature 1 (Japanese Patent Application Publication, Tokukaihei, No. 10-3782 (Publication Date: Jan. 6, 1998)) for example, in which a FIFO memory is a dual port memory including two memory circuits, and writing and reading of data are alternately carried out with respect to each of the two memory circuits.
However, in a conventional image processing apparatus including a plurality of types of image process sections for carrying out image processes by using image data with different numbers of lines, there has been such a problem that the size of a circuit of the image processing apparatus is increased. This is because, in such the conventional image processing apparatus, each of the image process sections needs to include a signal process circuit containing line buffers whose number corresponds to the number of lines for image data to be used by the image process section. Examples of the processes carried out by the plurality of types of the image process sections may encompass: a filter process (e.g., a filter process for carrying out smoothing or moire removal with respect to image data of a halftone dot region or image data of a background region); a segmentation process (e.g., an edge judgment process, a color judgment process, and a halftone dot judgment process); a rotation process; a zoom process; a labeling process; and a dilation/erosion process for removing an isolated point.
Further, in a case where the technique disclosed in Patent Literature 1 is applied to a line buffer of an image processing apparatus, it is necessary to reduce the number of storage words (the number of pixels of a signal to be stored) of each memory circuit included in an FIFO memory to half the number of pixels along a main scanning direction, for the purpose of equalizing the number of storage words between the memory circuits. Therefore, in a case of carrying out a plurality of image processes in which different numbers of words per line are stored in the memory circuit, it is impossible to share the FIFO memory between sections for carrying out the image processes. For this reason, the image process sections for carrying out the above-mentioned image processes are required to be provided with signal process circuits, one for each image process section, respectively. This increases the size of the circuit.